Aspects of semiconductor fabrication have focused on providing highly integrated semiconductor devices. Such semiconductor devices may include metal wirings on a circuit having a micro line width whereby the distance between the lines also becomes small. In order to reduce the size of the devices, a multi-layered wiring structure may be required. The multi-layered wirings may require a pre-metal dielectric (PMD) layer for providing electrical insulation between the metal lines.
The PMD layer for providing electrical isolation between the metal wirings may be formed by depositing undoped silicate glass (USG), TEOS or silicon nitride (SiH4) using a plasma enhanced chemical vapor deposition (PE-CVD) method. The PMD layer may alternatively be formed by depositing silicon oxide (SiO2) using a high density plasma (HDP CVD) method. The PMD layer may then be polished using a CMP process.
As illustrated in example FIG. 1A, isolation layers 12 defining an active region and an inactive region may be formed in silicon semiconductor substrate 10. Isolation layers 12 may be formed by etching semiconductor substrate 10 to a predetermined depth to form trenches. The trenches may be gap-filled with insulating material, such as an HDP oxide layer. The insulating material may then be polished using a CMP process to form shallow trench isolation (STI)-type isolation layers 12.
An insulating layer composed of SiO2 may be deposited having a thickness of approximately 100 Å on and/or over the entire uppermost surface of semiconductor substrate 10 in which isolation layers 12 are formed. A gate conductive layer composed of doped polysilicon into which an impurity has been doped, may be deposited to a thickness of approximately 3000 Å on and/or over the insulating layer. The gate conductive layer can be composed of at least one of silicon germanium (SiGe), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), or a composite thereof and doped polysilicon.
A photolithographic process may be performed to form a photoresist pattern defining a gate region in the gate conductive layer. A dry etch, such as reactive ion etching (RIE), may be performed on the gate conductive layer exposed by the pattern, thus forming gate electrode 16. A dry etch may also be performed on the underlying insulating layer to form gate insulating layer 14. The photoresist pattern may then be removed using an ashing process.
A low-concentration ion implantation process using an n-type dopant of a low concentration, may be performed by using gate electrode 16 as an ion implant mask, thus forming a lightly doped drain (LDD) region.
An insulating material composed of at least one of SiN and SiON, may be deposited over the entire uppermost surface of semiconductor substrate 10. A dry etch such as RIE may be performed on the insulating material to form a pair of spacers 18 on the sidewalls of gate electrode 16.
A high-concentration ion implantation process using an n-type dopant of a low concentration, may be performed using gate electrode 16 and spacers 18 as an ion implant mask, thus forming source/drain regions 20.
As illustrated in example FIG. 1B, etch-stop layer 22 composed SiN may be deposited having a thickness of between approximately 300 to 500 Å on and/or over the entire surface of the resultant semiconductor substrate structure in which a MOS transistor including gate electrode 16 and source/drain regions 20, is formed. Etch-stop layer 22 may serve to protect the underlying MOS transistor from infiltration of moving ions, moisture, etc. when subsequent processes are carried out, and also to stop etching with a high etch selectivity at the time of a contact formation process.
An insulating layer including first PMD layer 24 may be thickly deposited having a thickness of approximately 7000 Å or more on and/or over etch-stop layer 22. First PMD layer 24 may be composed of at least one of an O3-TEOS oxide layer, a BPSG insulating layer and a HDP CVD oxide layer having a good gap-fill characteristic. First PMD layer 24 may serve to gap-fill the space between the underlying semiconductor devices.
As illustrated in example FIG. 1C, a CMP process may be performed on first PMD layer 24 in order to polish the surface thereof, resulting in polished PMD layer 24a. Thereafter, a TEOS oxide layer composed of second PMD layer 26, may be deposited on and/or over polished first PMD layer 24a to a thickness of between 1000 to 2000 Å. Second PMD 26 may serve to cure the surface of the insulating layer, which is degraded by the CMP process of first PMD layer 24.
As illustrated in example FIG. 1D, a photolithographic process may be performed on second PMD 26, thus forming a photoresist pattern defining a contact region. A dry etch may be performed on etch-stop layer 22, first PMD layer 24a and second PMD layer 26, which are exposed by the photoresist pattern, to form a plurality of contact holes 28 which exposes the uppermost surface of source/drain regions 20. The photoresist pattern may then be removed by an ashing process. Reference numerals 22a, 24b, and 26a designate the etch-stop layer, the first PMD layer, and the second PMD layer, respectively, after formation of contact holes 28 using the dry etch.
As illustrated in example FIG. 1E, a conductive layer may be deposited to gap-fill contact holes 28. The conductive layer on and/or over the surface of second PMD layer 26a may be removed using a CMP process to form a plurality of contacts 30 vertically and electrically connected to source/drain regions 20. The conductive layer constituting contacts 30 can be composed of doped polysilicon, tungsten (W) or the like.
In the formation process of the PMD layers of the semiconductor device, if the contact holes are formed in the thin PMD, tungsten (W) may be deposited, and tungsten CMP may then be performed, erosion may occur in the alignment key pattern region “A.” This is due to the thickness of an insulating layer, such as PMD, is not sufficiently thick in terms of device characteristics. If the alignment key pattern “A” cannot be recognized, further processes cannot be performed.